lexer grammar VhdlLexer;

@header {
package org.moflon.moca.vhdl.parser;
import org.moflon.moca.MocaUtil;
}
// lexer rules:

VHDL: 'VHDL';
ENTITY:   'entity';
ARCHITECTURE: 'architecture';
GATE :    'gate';
BLOCK:    'block'; 
IS:       'is';
OF:       'of';
SIGNAL:   'signal';
BEGIN:    'begin';
END:      'end';
PORT:     'port ';
OPEN_PAREN: '(';
CLOSE_PAREN: ')';
SEMICOLON:  ';';
COMMA:      ',';
COLON:      ':';
ASSIGNMENT: '<=';
AND:        'and';
OR:         'or';
NOT:        'not';
PORT_MAP:   'port map';
MAP_SIGN:   '=>';

DIRECTION:  ('in' | 'out');

fragment DIGIT: '0'..'9';

fragment SMALL_LETTER: 'a'..'z';

fragment CAPITAL_LETTER: 'A'..'Z';

ID: (SMALL_LETTER | CAPITAL_LETTER | DIGIT | '_')+;

NL: ('\r'? '\n') { skip(); };

WS: (' ' | '\n' | '\r' | '\t')+ { skip(); };

